TMPR4955AF datasheet(154/168 Pages) TOSHIBA

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Chapter 9 Debug Support Unit

9-2

9.3

JTAG Interface

Standard JTAG interface is used for on chip debugging during Run Time mode. The TX49

Debug Support Unit has following registers.

• Instruction Register

• Bypass Register

• Boundary-Scan Register

• Device Identification Register

• Implementation Register

• JTAG_Data_Register

• JTAG_Address_Register

• JTAG_Control_Register

9.4

Processor Access Overview

The core processor can access external processor probe for reading and writing to external

monitor memory, registers and other external resources.

In addition the processor can execute from the external monitor memory located from

0xf_ff20 0000 to 0xf_ff2f ffff when the ProbEnb bit is set and the processor probe is turned ON.

Any access to the monitor location from 0xf_ff20 0000 to 0xf_ff3f ffff are only allowed when the

processor is in the debug mode (DM = 1).

9.5

Instruction

The instruction is a 8 bit field. Instructions for the TX49 Debug Support Unit are encoded

between 0x80 and 0x9f and other codes are reserved for Toshiba Standard JTAG instructions

(Includes EXTEST, SAMPLE/PRELOAD and IDCODE) and so on. Instructions are decoded as

follows.

Figure 9.5.1 Instruction

Hex Value

Instruction

Description

0x00

EXTEST

Boundary Scan Register

0x01

SAMPLE/PRELOAD

Boundary Scan Register

0x02

Reserve

0x03

IDCODE

Device Identification Register

0x83

EJTAG_ImpCode

Select Implementation Register

0x88

JTAG_ADDRESS_IR

Select JTAG_Address Register

0x89

JTAG_DATA_IR

Select JTAG_Data Register

0x8A

JTAG_CONTROL_IR

Select JTAG_Control Register

0x8B

JTAG_ALL_IR

Select JTAG_All Register

0x90

PCTRACE

PCIRACE Instruction

0xFF

BYPASS

Select BYPASS Register

Note: 0x80

∼ 0x9F the other code. Please does not used.

Any unused instruction between 0x80 and 0x9f defaulted to BYPASS instruction.

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