S75WS256NDFBAWMB datasheet(72/216 Pages) SPANSION

72 / 216 page

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

12.8.3

Timing Diagrams

Notes:

1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two

cycles to seven cycles.

2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and

are indicated by RDY.

3. The device is in synchronous mode.

Figure 12.7 CLK Synchronous Burst Mode Read

Da + 1

Da + n

OE#

Data (n)

Addresses

AVD#

RDY (n)

CLK

CE#

tCES

tACS

tAVC

tAVD

tACH

tOE

tRACC

tOEZ

tCEZ

tIACC

tAOE

tBDH

5 cycles for initial access shown.

18.5 ns typ. (54 MHz)

Hi-Z

tRDYS

tBACC

Da + 3

Da + 2

Da + 1

Da + n

Data (n + 1)

RDY (n + 1)

Hi-Z

Da + 2

Da + 1

Da + n

Data (n + 2)

RDY (n + 2)

Hi-Z

Da + 1

Da + n

Data (n + 3)

RDY (n + 3)

Hi-Z

tCR

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