S75WS256NDFBAWMB datasheet(145/216 Pages) SPANSION

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Publication Number S75WS-N-00

Revision A Amendment 0 Issue Date February 17, 2005

CellularRAM

128/64/32 Megabit

Burst CellularRAM

Features

Single device supports asynchronous, page,

and burst operations

VCC Voltages

— 1.70V–1.95V VCC

Random Access Time: 70ns

Burst Mode Write Access

— Continuous burst

Burst Mode Read Access

— 4, 8, or 16 words, or continuous burst

Page Mode Read Access

— Sixteen-word page size

— Interpage Read access: 70ns

— Intrapage Read access: 20ns

Low-Power Consumption

— Asynchronous Read < 25mA

— Intrapage Read < 15mA

— Initial access, burst Read < 35mA

— Continuous burst Read < 11mA

— Standby: 180µA

— Deep power-down < 10µA

Low-Power Features

— Temperature Compensated Refresh (TCR) On-chip

sensor control

— Partial Array Refresh (PAR)

— Deep Power-Down (DPD) Mode

General Description

CellularRAM™ products are High-speed, CMOS dynamic random access memories developed for low-

power, portable applications. These devices include an industry standard burst mode Flash interface that

dramatically increases Read/Write bandwidth compared with other low-power SRAM or Pseudo SRAM

offerings.

To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh

mechanism. The hidden refresh requires no additional support from the system memory controller and

has no significant impact on device Read/Write performance.

Two user-accessible control registers define device operation. The bus configuration register (BCR) de-

fines how the CellularRAM device interacts with the system memory bus and is nearly identical to its

counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how

refresh is performed on the DRAM array. These registers are automatically loaded with default settings

during power-up and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh. CellularRAM prod-

ucts include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the

system to limit refresh to only that part of the DRAM array that contains essential data. Temperature com-

pensated refresh (TCR) adjusts the refresh rate to match the device temperature—the refresh rate

decreases at lower temperatures to minimize current consumption during standby. Deep power-down

(DPD) enables the system to halt the refresh operation altogether when no vital information is stored in

the device. The system-configurable refresh mechanisms are accessed through the RCR.

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