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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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S75WS256NDFBAWMB 데이터시트(PDF) 200 Page - SPANSION |
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S75WS256NDFBAWMB 데이터시트(HTML) 200 Page - SPANSION |
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200 / 216 page  198 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Ad van c e Inf o rmation Table 34.15 Burst Write Timing Parameters Symbol 70ns/80 MHz 85ns/66 MHz Units Min Max Min Max tCBPH 55 ns tCEW 17.517.5 ns tCLK 12.5 15 ns tCSP 45 ns tHD 22 ns tHZ 88 ns tKHKL 1.6 1.6 ns tKHTL 911 ns tKP 33 ns tSP 33 ns Notes: 1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. 2. Wait will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status). Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Don't Care Legend: VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# WAIT tCLK VIH VIL CLK (Note 2) VIH VIL OE# tOHZ VIH VIL WE# tKHTL tKHTL VOH VOL DQ[15:0] tHD tSP Valid Input D[n] Valid Input D[n+1] Valid Input D[n+3] Valid Input D[n+2] END OF ROW |
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