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TMPR4925 데이터시트(PDF) 204 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 204 Page - Toshiba Semiconductor |
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204 / 590 page ![]() Chapter 8 DMA Controller 8-34 8.4.8 DMA Destination Address Increment Register (DMDAIRn) 0xB014 (ch. 0) 0xB034 (ch. 1) 0xB054 (ch. 2) 0xB074 (ch. 3) 31 24 23 16 Reserved DADINC[23:16] R/W : Type - : Initial value 15 0 DADINC[15:0] R/W : Type - : Initial value Bits Mnemonic Field Name Description 31:24 Reserved 23:0 DADINC Destination Address Increment Destination Address Increment (Initial value: undefined, R/W) This field sets the increase/decrease value of the DMA Destination Address Register (DMDARn). This value is a 24-bit two’s complement and indicates a byte count. Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Figure 8.4.8 DMA Destination Address Increment Register |
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