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TMPR4925 데이터시트(PDF) 205 Page - Toshiba Semiconductor |
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TMPR4925 데이터시트(HTML) 205 Page - Toshiba Semiconductor |
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205 / 590 page ![]() Chapter 8 DMA Controller 8-35 8.4.9 DMA Count Register (DMCNTRn) 0xB00C (ch. 0) 0xB02C (ch. 1) 0xB04C (ch. 2) 0xB06C (ch. 3) 31 26 25 16 Reserved DMCNTR[25:16] R/W : Type - : Initial value 15 0 DMCNTR[15:0] R/W : Type - : Initial value Bits Mnemonic Field Name Description 31:26 Reserved 25:0 DMCNTR Count Count Register (Initial value: undefined, R/W) This register sets the byte count that is transferred by the DMA Channel Register setting. The value is a 26-bit unsigned data that is decremented only by the size of the data transferred during a single bus operation. Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Figure 8.4.9 DMA Count Register |
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