Configuration
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
3-11
Fast context switch extension process identifier
Reading from CP15 register 13 with opcode_2=0 returns the value of the FCSE PID.
This is shown in Figure 3-11.
Figure 3-11 Register 13 with opcode_2=0
Note
Only bits [31:25] are returned. The remaining 25 bits are unpredictable.
Writing to CP15 register 13 with opcode_2=0 updates the FCSE PID from the value in
bits [31:25]. Bits [24:0] should be zero. The FCSE PID is set to b0000000 on Reset.
The CRm and opcode_2 should be zero when reading or writing the FCSE PID.
Changing FCSE PID
You must take care when changing the FCSE PID because the following instructions
have been fetched with the previous FCSE PID. In this way, changing the FCSE PID
has similarities with a branch with delayed execution. See Relocation of low virtual
addresses by the FCSE PID on page 2-22.
Trace process identifier
A 32-bit read/write register is provided to hold a Trace PROCess IDentifier (PROCID)
up to 32-bits in length visible to the ETM7. This is achieved by reading from or writing
to the CP15 register 13 with opcode_2 = 1 as shown in Figure 3-12.
Figure 3-12 Register 13 with opcode_2=1
Signal PROCIDWR is exported to notify the ETM7 that the Trace PROCID has been
written.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
FCSE PID
UNP/SBZ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Trace PROCID
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