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Instruction and Data Cache
4-4
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
4.2
IDC validity
The IDC operates with virtual addresses, so you must ensure that its contents remain
consistent with the virtual to physical mappings performed by the MMU. If the memory
mappings are changed, the IDC validity must be ensured.
4.2.1
Software IDC flush
The entire IDC can be marked as invalid by writing to the cache operations register R7.
The cache is flushed immediately the register is written, but the following two
instruction fetches can come from the cache before the register is written.
4.2.2
Doubly-mapped space
Because the cache works with virtual addresses, it is assumed that every virtual address
maps to a different physical address. If the same physical location is accessed by more
than one virtual address, the cache cannot maintain consistency. Each virtual address
has a separate entry in the cache, and only one entry can be updated on a processor write
operation.
To avoid any cache inconsistencies, both doubly-mapped virtual addresses must be
marked as uncachable.
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