µPD61P24

14

14. STANDBY FUNCTION (HALT INSTRUCTION)

The

µPD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,

when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).

In the standby mode, the program execution stops. However, the contents of the internal registers and the data

memory are all retained.

14.1

STOP Mode (Oscillation stop HALT instruction)

In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops.

Therefore, operations requiring the system clock will stop.

If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode

will be initiated, after the timer count down operation is completed.

14.2

HALT Mode (Oscillation continue HALT instruction)

The CPU stops its operation, until the HALT release condition is satisfied.

The system clock operation continues in this mode.

14.3

Standby Release Conditions

(1) S-IN input

(2) KI/O input

(3) KI input

(4) Timer count down operation completion

Remark

Either high level or low level can be specified for setting a release condition by input.

Table 14-1. Standby Mode Releasing Condition

D 3

0/1

0

Releasing condition:

0

1

Timer

01

00

K

0

0

S-IN

D 2

D 1

D 0

Releasing

Condition

1

0

1

0

I/O

K I

Remarks

Released when 0.

Valid only in the IN mode.

When RL

A is selected, the standby mode is

always released.

3

←

“0”···Low level detection

“1”···High level detection