PC7447AMGH1000LB datasheet(15/44 Pages) ATMEL

15 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

During operation, the die-junction temperatures (T

j) should be maintained less than the value

specified in Table 6-2 on page 10. The temperature of air cooling the component greatly

depends on the ambient inlet air temperature and the air temperature rise within the electronic

cabinet. An electronic cabinet inlet-air temperature (T

i) may range from 30° to 40°C. The air tem-

perature rise within a cabinet (T

r) may be in the range of 5° to 10°C. The thermal resistance of

the thermal interface material (Rθint) is typically about 1.5°C/W. For example, assuming a Ti of

°C, a T

r of 5°C, an HITCE package R

θJC = 0.1, and a typical power consumption (Pd) of

18.7W, the following expression for T

j is obtained:

Die-junction temperature: T

j = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7W

For this example, a Rθsa value of 2.1°C/W or less is required to maintain the die junction temper-

ature below the maximum value of Table 6-2 on page 10.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a com-

mon figure-of-merit used for comparing the thermal performance of various microelectronic

packaging technologies, one should exercise caution when only using this metric in determining

thermal management because no single parameter can adequately describe three-dimensional

heat flow. The final die-junction operating temperature is not only a function of the component-

level thermal resistance, but the system-level design and its operating conditions. In addition to

the component's power consumption, a number of factors affect the final operating die-junction

temperature – airflow, board population (local heat flux of adjacent components), heat sink effi-

ciency, heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, and so on.

Due to the complexity and variety of system-level boundary conditions for today's microelec-

tronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,

and conduction) may vary widely. For these reasons, we recommend using conjugate heat

transfer models for the board, as well as system-level designs.

For system thermal modeling, the PC7447A thermal model is shown in Figure 6-5 on page 16.

Four volumes represent this device. Two of the volumes, solder ball-air and substrate, are mod-

eled using the package outline size of the package. The other two, die, and bump-underfill, have

the same size as the die. The silicon die should be modeled 9.5 × 9.5 × 0.7 mm with the heat

source applied as a uniform source at the bottom of the volume. The bump and underfill layer is

modeled as 7.3 × 9.3 × 0.7 mm (or as a collapsed volume) with orthotropic material properties:

0.6 W/(m × K) in the xy-plane and 1.9 W/(m × K) in the direction of the z-axis. The substrate vol-

ume is 25 × 25 × 1.2 mm, and has 8.1 W/(m × K) isotropic conductivity in the xy-plane and 4

W/(m × K) in the direction of the z-axis. The solder ball and air layer are modeled with the same

horizontal dimensions as the substrate and are 0.6 mm thick. They can also be modeled as a

collapsed volume using orthotropic material properties: 0.034 W/(m × K) in the xy-plane direction

and 3.8 W/(m × K) in the direction of the z-axis.

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