PC7447AMGH1000LB datasheet(3/44 Pages) ATMEL

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5387B–HIREL–07/05

PC7447A [Preliminary]

2. General Parameters

Table 2-1 provides a summary of the general parameters of the PC7477A.

3. Features

This section summarizes features of the PC7447A implementation of the PowerPC architecture.

Major features of the PC7447A are as follows:

• High-performance, superscalar microprocessor

– Up to four instructions can be fetched from the instruction cache at a time

– Up to 12 instructions can be in the instruction queue (IQ)

– Up to 16 instructions can be at some stage of execution simultaneously

– Single-cycle execution for most instructions

– One instruction per clock cycle throughput for most instructions

– Seven-stage pipeline control

• Eleven independent execution units and three register files

– Branch processing unit (BPU) features static and dynamic branch prediction

128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC),

a cache of branch instructions that have been encountered in branch/loop code

sequences. If a target instruction is in the BTIC, it is fetched into the instruction

queue a cycle sooner than it can be made available from the instruction cache.

Typically, a fetch that hits the BTIC provides the first four instructions in the target

stream.

2048-entry branch history table (BHT) with two bits per entry for four levels of

prediction: not taken, strongly not taken, taken, and strongly taken

Up to three outstanding speculative branches

Branch instructions that do not update the count register (CTR) or link register (LR)

are often removed from the instruction stream

Table 2-1.

Device Parameters

Parameter

Description

Technology

0.13 µm CMOS, nine-layer metal

Die size

8.51 mm × 9.86 mm

Transistor count

48.6 million

Logic design

Fully-static

Packages

Surface mount 360 ceramic ball grid array

(HITCE)

Core power supply

1.3V ±50 mV DC nominal

I/O power supply

1.8V ±5% DC, or 2.5V ±5% DC

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