Si53112

12

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 2, 2021

2.4. SA_0, SA_1—Address Selection

SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53112. The two tri-

level input pins that can configure the device to nine different addresses.

2.5. PWRGD/PWRDN

PWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to

indicating a power-down condition. PWRGD (assertion) is used by the Si53112 to sample initial configurations,

such as frequency select condition and SA selections. After PWRGD has been asserted high for the first time, the

pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to

invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering power-saving

mode, PWRDN should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down

in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO. When

PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all ac and dc

parameters.

Note: The assertion and deassertion of PWRDN is absolutely asynchronous.

Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.

Operation in this mode may result in glitches, excessive frequency shifting, etc.

Table 11. SMBUS Address Table

SA_1

SA_0

SMBUS Address

LL

D8

LM

DA

LH

DE

ML

C2

MM

C4

MH

C6

HL

CA

HM

CC

HH

CE

Table 12. PWRGD/PWRDN Functionality

PWRGD/PWR

DN

DIF

DIF

0

Low

Low

1Normal

Normal