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STE10A 데이터시트(PDF) 75 Page - STMicroelectronics |
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STE10A 데이터시트(HTML) 75 Page - STMicroelectronics |
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75 / 82 page ![]() STE10/100A Electrical specifications and timings 75/82 Figure 17. PCI timings Table 23. Flash interface timings Symbol Parameter Test condition Min. Typ. Max. Units Tfcyc Read/write cycle time ns Tfce Address to read data setup time ns Tfce CS# to read data setup time ns Tfoe OE# active to read data setup time ns Tfdf OE# inactive to data driven delay time ns Tfas Address setup time before WE# ns Tfah Address hold time after WE# ns Tfcs CS# setup time before WE# ns Tfch Address hold time after WE# ns Tfds Data setup time ns Tfdh Data hold time ns Tfwpw Write pulse width ns Tfwph Write pulse width high ns Tfasc Address setup time before CS# ns Tfahc Address hold time after CS# ns CLK 0.6Vcc 0.2Vcc Tval OUTPUT delay Ton 0.4Vcc Tri-state OUTPUT INPUT 0.4Vcc Toff Tsu Th . 0.4Vcc 0.6Vcc 0.2Vcc 0.4Vcc 0.4Vcc |
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