STE10A datasheet(18/82 Pages) STMICROELECTRONICS

18 / 82 page

Functional description

STE10/100A

18/82

3.3.2

Transmit pre-fetch data flow

–

Transmit FIFO size=2K-byte

–

Two packets in the FIFO at the same time

–

Meet the transmit min. back-to-back

Figure 10.

Transmit pre-fetch data flow

3.3.3

Transmit early interrupt scheme

Figure 11.

Transmit normal interrupt and early interrupt comparison

Place the 1st packet data into host memory

Issue transmit demand

FIFO-to-host memory operation (1st packet)

Time

Transmit enable

Place the 2nd packet data into host memory

Check the

next packet

Check point

FIFO-to-host memory operation (2nd packet)

Transmit

threshold

Place the 3rd packet data into host memory

1st packet is

transmitted, check

the 3rd packet

FIFO-to-host memory operation (3rd packet)

IFG

Check point

1st packet

2nd packet

: handled by driver

: handled by STE10/100A

PC00355

Host to TX-FIFO memory

operation

Transmit data from FIFO to media

Normal interrupt after transmit

completed

Driver return buffer to upper layer

Early interrupt after host to TX-

FIFO operation completed

Driver return buffer to upper layer

The saved time when transmit

early interrupt is implemented

Time

: handled by driver

: handled by STE10/100A

Host to TX-FIFO memory

operation

Transmit data from FIFO to media

Normal interrupt after transmit

completed

Driver return buffer to upper layer

Early interrupt after host to TX-

FIFO operation completed

Driver return buffer to upper layer

The saved time when transmit

early interrupt is implemented

Time

: handled by driver

: handled by STE10/100A

PC00356

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