PSD835G2 datasheet(62/102 Pages) STMICROELECTRONICS

62 / 102 page

PSD835G2

62/102

Table 36. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port E.

4. Control Register setting is not applicable to Ports A, B and C.

Table 37. I/O Port Latched Address Output Assignments

Note: 1. N/A = Not Applicable.

Mode

Defined in PSDsoft

Control

Setting

Direction

Setting

VM Register

Setting

JTAG Enable

MCU I/O

Declare pins only

0 (Note 4)

1 = output,

0 = input

(Note 2)

N/A

PLD I/O

Declare pins and logic

equations

N/A

(Note 2)

N/A

Data Port (Port F)

Selected for MCU with

non-mux bus

N/A

Address Out

(Port E, F, G)

Declare pins only

1 (Note 2)

N/A

Address In

(Port A,B,C,D, F)

Declare pins or logic

equations for Input

Macrocells

N/A

Peripheral I/O

(Port F)

Logic equations

(PSEL0 & 1)

N/A

PIO Bit = 1

N/A

JTAG ISP (Note 3)

Declare pins only

N/A

JTAG_Enable

MCU

Port E

(PE3-PE0)

Port E

(PE7-PE4)

Port F

(PF3-PF0)

Port F

(PF7-PF4)

Port G

(PG3-PG0)

Port G

(PG7-PG4)

8051XA

N/A1

Address

(A7-A4)

N/A1

Address

(A7-A4)

Address

(A11-A8)

Address

(A15-A12)

80C251

(Page Mode)

N/A

Address

(A11-A8)

Address

(A7-A4)

All Other

8-Bit Multiplexed

Address

(A3-A0)

Address

(A7-A4)

Address

(A3-A0)

Address

(A7-A4)

Address

(A3-A0)

Address

(A7-A4)

8-Bit

Non-Multiplexed Bus

N/A

Address

(A3-A0)

Address

(A7-A4)

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