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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PSD835G2 데이터시트(PDF) 67 Page - STMicroelectronics |
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PSD835G2 데이터시트(HTML) 67 Page - STMicroelectronics |
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67 / 102 page  67/102 PSD835G2 Port D – Functionality and Structure Port D has four I/O pins. It can be configured to program one or more of the following functions (see Figure 29): – MCU I/O Mode – CPLD Input – direct input to CPLD, no Input Macrocell (IMC). Port D pins can be configured in PSDsoft as input pins for other dedicated functions: – PD0 – ALE, as Address Strobe input. – PD1 – CLKIN, as Clock input to the Macrocell flip-flops and APD counter. – PD2 – CSI, as active Low Chip Select input. A High input will disable the Flash/SRAM memories and the CSIOP. – PD3 – as DBE input from 68HC912. Figure 29. Port D Structure DATA OUT REG. DQ DQ WR WR READ MUX P D B CPLD - INPUT DIR REG. DATA IN OUTPUT SELECT OUTPUT MUX PORT D PIN DATA OUT AI02888C |
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