PSD835G2 datasheet(17/102 Pages) STMICROELECTRONICS

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PSD835G2

JTAG Port

In-System Programming (ISP) can be performed

through the JTAG signals on Port E. This serial in-

terface allows complete programming of the entire

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR, TDI, TDO) can be multiplexed with

other functions on Port E. Table 3., page 16 indi-

cates the JTAG pin assignments.

In-System Programming (ISP)

Using the JTAG signals on Port E, the entire PSD

device (memory, logic, configuration) can be pro-

grammed or erased without the use of the MCU.

In-Application re-Programming (IAP)

The primary Flash memory can also be pro-

grammed in-system by the MCU executing the

programming algorithms out of the secondary

memory, or SRAM. Since this is a sizable separate

block, the application can also continue to operate.

The secondary memory can be programmed the

same way by executing out of the primary Flash

memory. The PLD or other PSD Configuration

blocks can be programmed through the JTAG port

or a device programmer. Table 4 indicates which

programming methods can program different func-

tional blocks of the PSD.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the

user control of the power consumption on selected

functional blocks based on system requirements.

The PMU includes an Automatic Power-down

(APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down

mode that helps reduce power consumption.

The PSD also has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to ’0’ and the CPLD latches its outputs and

goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the

MCU to block signals from entering the CPLD to

reduce power consumption. Please see POWER

MANAGEMENT, page 70 for more details.

Table 4. Methods of Programming Different Functional Blocks of the PSD

Functional Block

JTAG/ISP

Device Programmer

IAP

Primary Flash Memory

Yes

Secondary Flash Memory

Yes

PLD Array (DPLD and CPLD)

Yes

PSD Configuration

Yes

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