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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PSD835G2 데이터시트(PDF) 85 Page - STMicroelectronics |
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PSD835G2 데이터시트(HTML) 85 Page - STMicroelectronics |
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85 / 102 page  85/102 PSD835G2 Figure 38. Input to Output Disable / Enable Figure 39. Combinatorial Timing – PLD Table 58. CPLD Combinatorial Timing Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Symbol Parameter Conditions -70 -90 PT Aloc Turbo Off Slew rate1 Unit Min Max Min Max tPD CPLD Input Pin/Feedback to CPLD Combinatorial Output 20 25 + 2 + 12 – 2 ns tEA CPLD Input to CPLD Output Enable 21 26 + 12 – 2 ns tER CPLD Input to CPLD Output Disable 21 26 + 12 – 2 ns tARP CPLD Register Clear or Preset Delay 21 26 + 12 – 2 ns tARPW CPLD Register Clear or Preset Pulse Width 10 20 + 12 ns tARD CPLD Array Delay Any macrocell 11 16 + 2 ns tER tEA INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863 tPD CPLD OUTPUT CPLD INPUT AI07655 |
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