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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PSD835G2 데이터시트(PDF) 73 Page - STMicroelectronics |
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PSD835G2 데이터시트(HTML) 73 Page - STMicroelectronics |
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73 / 102 page  73/102 PSD835G2 Input Control Signals The PSD provides the option to turn off the ad- dress input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/ AS, PD0) and DBE) to the PLD to save AC power consumption. These signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 0, 2, 3, 4, 5, and 6 to a ‘1’ in PMMR2. Table 46. APD Counter Operation APD Enable Bit ALE PD Polarity ALE Level APD Counter 0 X X Not Counting 1 X Pulsing Not Counting 1 1 1 Counting (Generates PDN after 15 Clocks) 1 0 0 Counting (Generates PDN after 15 Clocks) |
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