AMC131M01DFMR datasheet(73/81 Pages) TI

73 / 81 page

9.4.2 Layout Example

Figure 9-9 shows an example layout of the AMC131M01 requiring a minimum of two PCB layers. In general,

analog and digital signals for the primary (low) side are partitioned to the right and analog and digital signals for

the secondary (high) side are on the left.

3: HLDO_IN

5: HGND

7: NC

8: NC

9: AIN0P

+3.3 V

TI Device

+3.3 V

Via to corresponding

voltage plane or pour

Via

Differential RC-filter

for input channel.

Terminate long digital

input lines with resistors to

prevent reflection.

Channel 0

20: DIN

19: CS

18: SCLK

17: CLKIN

16: DRDY

14: DCDC_CAP

Clearance area, to be

kept free of any conductive

material.

4: HLDO_OUT

2: DCDC_HGND

1: DCDC_OUT

10: AIN0N

Place bypass

capacitor directly

across ADC inputs.

GPO

6: GPO

15: DGND

Place DCDC_CAP and power

supply decoupling capacitors close

to pins.

Place smaller decoupling

caps closest to the

device.

Place smaller decoupling

caps closest to the

device.

13: DVDD

12: DOUT

11: SYNC/RST

Top Metal

Inner or Bottom

Layer Metal

Keep layout of

shunt connections

symmetrical.

Use separate trace for HGND

connection to shunt terminal.

C11

C13

C10

C24

C17

C15

C16

GND

ISO_GND

Place ferrites

Close to the device

to improve EMI

performance.

Figure 9-9. Layout Example

www.ti.com

AMC131M01

SBASA57 – SEPTEMBER 2023

Submit Document Feedback

Product Folder Links: AMC131M01

AMC131M01DFMR 데이터시트(PDF) 73 Page - Texas Instruments

AMC131M01DFMR 데이터시트(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

데이터시트 다운로드

링크 URL