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AMC131M01DFMR 데이터시트(PDF) 10 Page - Texas Instruments

부품명 AMC131M01DFMR
상세설명  AMC131M01 1-Channel, 64-kSPS, Simultaneous-Sampling, 24-Bit, Reinforced Isolated Delta-Sigma ADC With Integrated DC/DC Converter
PDF  81 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

AMC131M01DFMR 데이터시트(HTML) 10 Page - Texas Instruments

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6.9 Timing Requirements
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
MIN
MAX
UNIT
3.0 V ≤ DVDD ≤ 5.5 V
tw(CLL)
Pulse duration, CLKIN low
49
ns
tw(CLH)
Pulse duration, CLKIN high
49
ns
tc(SC)
SCLK period
40
ns
tw(SCL)
Pulse duration, SCLK low
20
ns
tw(SCH)
Pulse duration, SCLK high
20
ns
td(CSSC) Delay time, first SCLK rising edge after CS falling edge
16
ns
td(SCCS) Delay time, CS rising edge after final SCLK falling edge
10
ns
tw(CSH)
Pulse duration, CS high
15
ns
tsu(DI)
Setup time, DIN valid before SCLK falling egde
5
ns
th(DI)
Hold time, DIN valid after SCLK falling edge
8
ns
tw(SYL)
Pulse duration, SYNC/RESET low for synchronization
1
2047
tCLKIN
tw(RSL)
Pulse duration, SYNC/RESET low to generate device reset
2048
tCLKIN
tsu(SY)
Setup time, SYNC/RESET valid before CLKIN falling edge
10
ns
6.10 Switching Characteristics
over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.0 V ≤ DVDD ≤ 5.5 V
tp(CSDO)
Propagation delay time, CS falling edge to
DOUT driven
50
ns
tp(SCDO)
Progapation delay time, SCLK rising edge to
valid new DOUT
20
ns
tp(CSDOZ)
Propagation delay time, CS rising edge to DOUT
high impedance
75
ns
tw(DRH)
Pulse duration, DRDY high
4
tCLKIN
tw(DRL)
Pulse duration, DRDY low
4
tCLKIN
tPOR
Power-on-reset time
Measured from supplies at
90%
250
µs
SPI timeout
32768
tCLKIN
tREGACQ Register default acquisition time
5
µs
AMC131M01
SBASA57 – SEPTEMBER 2023
www.ti.com
10
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AMC131M01



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