AMC131M01DFMR datasheet(21/81 Pages) TI

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device tolerance and change over temperature. Minimize the output impedance of the circuit that drives the

AMC131M01 inputs to obtain the best possible gain error, INL, and distortion performance.

275 kΩ × 4.096 MHz / fMOD

(4)

where:

• fMOD is the ΔΣ modulator frequency, fCLKIN / NDIV

By default, NDIV = 2. NDIV is set by the programmable clock divider, see the Clocking and Power Modes section.

The device uses an input precharge buffer for PGA gain settings of 8 and higher. The input impedance at these

gain settings is very high. Specifying the input bias current for these gain settings is therefore more useful.

8.3.7 Voltage Reference

The AMC131M01 uses an internally generated, low-drift, band-gap voltage to supply the reference for the ADC.

The reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V to 1.2 V.

The reference circuitry starts up very quickly to accommodate the fast start-up feature of this device. The device

waits until the reference circuitry is fully settled before generating conversion data.

8.3.8 Internal Test Signals

The AMC131M01 features an internal analog test signal that is useful for troubleshooting and diagnosis. A

positive or negative DC test signal can be applied to the channel inputs through the input multiplexer. The

multiplexer is controlled through the MUX0[1:0] bits in the CH0_CFG register. The test signals are created by

internally dividing the reference voltage.

The test signal is nominally 2 / 15 × VREF. The test signal automatically adjusts the voltage level with the gain

setting such that the ADC always measures a signal that is 2 / 15 × VDiff Max. For example, at a gain of 1, this

voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV.

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AMC131M01

SBASA57 – SEPTEMBER 2023

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AMC131M01DFMR 데이터시트(PDF) 21 Page - Texas Instruments