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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VC0736 데이터시트(PDF) 31 Page - NEXTCHIP Co,Ltd |
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VC0736 데이터시트(HTML) 31 Page - NEXTCHIP Co,Ltd |
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31 / 127 page  NVP6124 Data sheet 02.11.2015 (REV 0.2) 29/125 4-CH AHD2.0 RX and 9-CH Audio Codec DSP/SSP/I2S interfaces are supported by configuration of these pins defined by internal register setting value. Figure 3.1, 3.2, 3.3 shows timing diagram of I2S, DSP, and SSP mode, respectively. These figures show timing relation among ASYNC_REC, ACLK_REC and ADTA_REC, and ADATA_SP is outputted using same interface method of ADATA_REC. Polarity of ACLK_REC clock is changed by setting of internal register value (RM_CLK, 0x07[6], BANK1). MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.1 I2S mode MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.2 DSP mode MSB MSB 1/fs data0 data1 ASYNC_REC ACLK_REC ADATA_REC Figure 3.3 SSP mode |
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