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NVP6124

Data sheet

02.11.2015 (REV 0.2)

15/125

4-CH AHD2.0 RX and 9-CH Audio Codec

2.8. Data Output Order & Direction Control

NVP6124 can change the order of the output pin in the All Output Mode as shown in Table 2.2.

(OUT_DATA_INV, 0xD2[5:2] Bank1) Furthermore, as Clock and Data pins control direction so may it

does nothing with interconnected back-end device and how control related control register as shown

in Table 2.3. ( VCLK_x_EN, 0xCA[7:5] Bank1 / VDO_x_EN, 0xCA[3:1] Bank1 )

Table 2.2. Data Output Pin Order Control

Address (Bank1)

state

Data Output of Port X

0xD2, OUT_DATA_INV[5]

VDO4[7:0]

VDO4[0:7]

0xD2, OUT_DATA_INV[4]

VDO3[7:0]

VDO3[0:7]

0xD2, OUT_DATA_INV[3]

VDO2 [7:0]

VDO2 [0:7]

0xD2, OUT_DATA_INV[2]

VDO1 [7:0]

VDO1 [0:7]

Table 2.3. Output Clock and Data Direction Control

Address (Bank1)

state

Data Output of Port X

0xCA[4],VCLK_1_EN

0xCA[0], VDO_1_EN

High

’z

Output Enable

0xCA[5],VCLK_2_EN

0xCA[1], VDO_2_EN

High

’z

Output Enable

0xCA[6],VCLK_3_EN

0xCA[2], VDO_3_EN

High

’z

Output Enable

0xCA[7],VCLK_4_EN

0xCA[3], VDO_4_EN

High

’z

Output Enable

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