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NVP6124

Data sheet

02.11.2015 (REV 0.2)

20/125

4-CH AHD2.0 RX and 9-CH Audio Codec

2.10.2

2-Multiplex Output Mode

In the 2-Multiplex Output Mode, NVP6124 output multiplexed 2-channels video through in a

port. Figure2.13 shown as multiplexed with 2-channels video output to VDO1~VDO4. For

VCLK1, VCLK2, VCLK3 and VCLK4 phase adjustment can be made against VDO1~VDO4

using "Clock Delay Control" Register.

- (VCLK_x_SEL, 0xCC~CF[6:4], Control of Output Clock)

- (VCLK_x_DLY_SEL, 0xCC~CF[3:0], Control of Phase in Output Clock)

- (CH_OUT_SELx, 0xC8, 0xC9, Control how many multiplexed channel in a port)

CH2

CH1

CH2

CH1

CH2

All Port

(VDO1, VDO2, VDO3, VDO4)

Channel 1,2 data muxed @ 54MHz

/ 72MHz

/ 74.25MHz

/ 144MHz

/ 148.5MHz

CH1

CH2

Separated data 1

Separated data 2

Muxing

ch1~4

ch1

time

multiplexer

VDOx

CHx_OUT_SEL

VCLK0x

VPORTx_SEQx

Muxing

ch1~4

ch2

Muxing

ch1~4

ch3

Muxing

ch1~4

ch4

data of CH1

data of mixed CH1,2

data of mixed CH1,2,3,4

CHx_OUT_SEL

VDOx

54/72/74.25/148.5MHz Clock

(VCLK1, VCLK2,VCLK3,VCLK4)

Figure 2.13. Block Diagram of Multiplexed 2-Channels Output

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