AD9957SLASHPCBZ datasheet(32/60 Pages) AD

32 / 60 page

AD9957

Rev. 0 | Page 32 of 60

START ADDRESS

END ADDRESS

RAM ADRESS

1 PDCLK CYCLE

M DDS CLOCK CYCLES

I/O_UPDATE OR

RT TRANSITION

Figure 46. Continuous Recirculate Timing Diagram

RAM Continuous Recirculate Mode

The continuous recirculate mode mimics ramp-up mode,

except that when the state machine reaches the end address of

the active RAM segment register, it does not halt. Instead, the

next timeout of the internal timer causes the state machine to

jump to the start address of the active RAM segment register.

This process continues indefinitely until an I/O update or state

change on the RT pin. A state change on the RT pin aborts the

current waveform and the newly selected RAM segment register

initiates a new waveform.

A graphic representation of the continuous recirculate mode is

shown in Figure 46.

The circled numbers in Figure 46 indicate specific events, which

are explained as follows:

Event 1—an I/O update or state change on the RT pin occurs.

This initializes the state machine to the start address of the

active RAM segment register and causes the state machine to

begin incrementing the address counter at the appropriate rate.

Event 2—the state machine reaches the end address of the active

RAM segment register.

Event 3—the state machine switches to the start address of the

active RAM segment register. The state machine continues to

increment the address counter.

Event 4—the state machine again reaches the end address of the

active RAM segment register.

Event 5—the state machine switches to the start address of the

active RAM segment register. The state machine continues to

increment the address counter.

Event 4 and Event 5 repeat until an I/O update or state change

occurs on the RT pin.

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