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AD9957/PCBZ 데이터시트(PDF) 13 Page - Analog Devices

부품명 AD9957/PCBZ
상세설명  1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
PDF  60 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9957/PCBZ 데이터시트(HTML) 13 Page - Analog Devices

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AD9957
Rev. 0 | Page 13 of 60
–50
–55
–60
–65
–75
–70
FREQUENCY OUT (MHz)
SFDR WITHOUT PLL
SFDR WITH PLL
0
50
100
150
200
250
300
350
400
Figure 17. Wideband SFDR vs. Output Frequency in Single Tone Mode, PLL
with REFCLK = 15.625 MHz × 64
400
450
300
250
350
200
150
100
50
0
FREQUENCY OUT (MHz)
–75
–70
–65
–60
–55
–45
–50
LOW SUPPLY
HIGH SUPPLY
Figure 18. SFDR vs. Output Frequency vs. Supply (±5%) in Single Tone Mode
400
450
300
250
350
200
150
100
50
0
FREQUENCY OUT (MHz)
–75
–70
–65
–60
–55
–50
–40°C
+85°C
Figure 19. SFDR vs. Temperature in Single Tone Mode
–90
–100
–120
–110
–140
–150
–130
–170
–160
10
100
1k
10k
100k
100M
1M
10M
FREQUENCY OFFSET (Hz)
fOUT = 20.1MHz
fOUT = 98.6MHz
fOUT = 201.1MHz
fOUT = 397.8MHz
Figure 20. Residual Phase Noise, System Clock = 1 GHz
–90
–100
–110
–120
–130
–140
–150
–160
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
fOUT = 20.1MHz
fOUT = 397.8MHz
fOUT = 98.6MHz
fOUT = 201.1MHz
Figure 21. Residual Phase Noise Using the REFCLK Multiplier,
REFCLK = 50 MHz with 20x Multiplication, System Clock = 1 GHz
1200
200
400
600
800
1000
0
100
200
300
400
500
600
700
800
900
1000
SYSTEM CLOCK FREQUENCY (MHz)
DVDD 3.3V
AVDD 3.3V
AVDD 1.8V
DVDD 1.8V
Figure 22. Power Dissipation vs. System Clock (PLL Disabled)



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