AD9957SLASHPCBZ datasheet(18/60 Pages) AD

18 / 60 page

AD9957

Rev. 0 | Page 18 of 60

INTERPOLATING DAC MODE

A block diagram of the AD9957 operating in the interpolating

DAC mode is shown in Figure 28; grayed items are inactive. In

this mode, the Q data path, DDS, and modulator are all disabled;

only the I data path is active.

As in quadrature modulation mode, the PDCLK pin functions

as a clock, synchronizing the input of data to the AD9957.

No modulation takes place in the interpolating DAC mode;

therefore, the spectrum of the data supplied at the parallel port

remains at baseband. However, a sample rate conversion takes

place based on the programmed interpolation rate. The inter-

polation hardware processes the signal, effectively performing

an oversample with a zero-stuffing operation. The original

input spectrum remains intact and the images that otherwise

would occur from the sample rate conversion process are

suppressed by the interpolation signal chain.

PDCLK

I/Q IN

DAC_RSET

IOUT

TxENABLE

DAC GAIN

CLOCK

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMING AND CONTROL

AD9957

cos (ωt+θ)

sin (ωt+θ)

DDS

AUX

DAC

8-BIT

POWER

DOWN

CONTROL

OSK

INTERNAL CLOCK TIMING AND CONTROL

DAC

14-BIT

FTW

RAM

SERIAL I/O

PORT

PROGRAMMING

REGISTERS

IS QS

OUTPUT

SCALE

FACTOR

Figure 28. Interpolating DAC Mode

AD9957/PCBZ 데이터시트(PDF) 18 Page - Analog Devices

AD9957/PCBZ 데이터시트(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

데이터시트 다운로드

링크 URL