AD9957SLASHPCBZ datasheet(16/60 Pages) AD

16 / 60 page

AD9957

Rev. 0 | Page 16 of 60

QUADRATURE MODULATION MODE

A block diagram of the AD9957 operating in QDUC mode is

shown in Figure 26; grayed items are inactive. The parallel input

accepts 18-bit I- and Q-words in time-interleaved fashion. That

is, an 18-bit I-word is followed by an 18-bit Q-word, then the

next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit

Q-word together comprise one internal sample. The data

assembler and formatter de-interleave the I- and Q-words so

that each sample propagates along the internal data pathway in

parallel fashion. Both I and Q data paths are active; the parallel

data clock (PDCLK) serves to synchronize the input of I/Q data

to the AD9957.

The PROFILE and I/O_UPDATE pins are also synchronous to

the PDCLK.

The DDS core provides a quadrature (sine and cosine) local

oscillator signal to the quadrature modulator, where the

interpolated I and Q samples are multiplied by the respective

phase of the carrier and summed together, producing a

quadrature modulated data stream. This data stream is routed

through the inverse sinc filter (optionally), and the output

scaling multiplier. Then it is applied to the 14-bit DAC to

produce the quadrature modulated analog output signal.

PDCLK

I/Q IN

DAC_RSET

IOUT

TxENABLE

DAC GAIN

OUTPUT

SCALE

FACTOR

CLOCK

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

AD9957

cos (ωt+θ)

sin (ωt+θ)

DDS

AUX

DAC

8-BIT

POWER

DOWN

CONTROL

OSK

INTERNAL CLOCK TIMING AND CONTROL

DAC

14-BIT

FTW

PARALLEL DATA

TIMING AND CONTROL

RAM

SERIAL I/O

PORT

PROGRAMMING

REGISTERS

IS QS

Figure 26. Quadrature Modulation Mode

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