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XRT86VL34 데이터시트(PDF) 39 Page - Exar Corporation |
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XRT86VL34 데이터시트(HTML) 39 Page - Exar Corporation |
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39 / 156 page ![]() XRT86VL34 34 REV. V1.2.0 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0Xn116 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 TxSB_ISFIFO R/W 0 Transmit Slip Buffer Mode This bit permits the user to configure the Transmit Slip Buffer to function as either “Slip-Buffer” Mode, or as a “FIFO”, as depicted below. 0 - Configures the Transmit Slip Buffer to function as a “Slip-Buffer”. 1 - Configures the Transmit Slip Buffer to function as a “FIFO”. NOTE: Transmit slip buffer is only used in high-speed or multiplexed mode where TxSERCLKn must be configured as inputs only. Users must make sure that the “Transmit Direction” timing (i.e. TxMSYNC) and the TxSerClk input clock signal are synchronous to prevent any transmit slips from occuring. NOTE: The data latency is dictated by FIFO Latency in the FIFO Latency Register (register 0xn117). 6-5 Reserved - - Reserved 4 SB_FORCESF R/W 0 Force Signaling Freeze This bit permits the user to freeze any signaling update on the RxSIGn output pin as well as the Receive Signaling Array Register -RSAR (0xn500-0xn51F) until this bit is cleared. 0 = Signaling on RxSIG and RSAR is updated immediately. 1 = Signaling on RxSIG and RSAR is not updated until this bit is set to ‘0’. 3 SB_SFENB R/W 0 Signal Freeze Enable Upon Buffer Slips This bit enables signaling freeze for one multiframe after the receive buffer slips. If signaling freeze is enabled, then the “Receive Channel” will freeze all sig- naling updates on RxSIG pin and RSAR (0xn500-0xn51F) for at least “one- multiframe” period, after a “slip-event” has been detected within the “Receive Slip Buffer”. 0 = Disables signaling freeze for one multi-frame after receive buffer slips. 1 = Enables signaling freeze for one multi-frame after receive buffer slips. 2 SB_SDIR R/W 1 Slip Buffer (RxSync) Direction Select This bit permits user to select the direction of the receive frame boundary (RxSYNC) signal if the receive buffer is enabled. (i.e. SB_ENB[1:0] = 01 or 10). If slip buffer is bypassed, RxSYNC is always an output pin. 0 = Selects the RxSync signal as an output 1 = Selects the RxSync signal as an input |
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