SST25WF080B datasheet(18/44 Pages) MICROCHIP

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SST25WF080B

DS20005164H-page 18

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5.12

Write STATUS Register (WRSR)

The Write STATUS Register instruction writes new val-

ues to the BP0, BP1, BP2, TB, and BPL bits of the STA-

TUS register. CE# must be driven low before the

command sequence of the WRSR instruction is entered

and driven high before the WRSR instruction is exe-

cuted. Poll the BUSY bit in the Software STATUS reg-

ister, or wait TWRSR, for the completion of the internal

self-timed Write STATUS Register cycle. See Figure 5-

12 for WREN and WRSR instruction sequences and Fig-

ure 6-11 for the WRSR flow chart.

Executing the Write STATUS Register instruction will

be ignored when WP# is low and BPL bit is set to ‘1’.

When the WP# is low, the BPL bit can only be set from

‘0’ to ‘1’ to lock-down the STATUS register, but cannot

be reset from ‘1’ to ‘0’. When WP# is high, the lock-

down function of the BPL bit is disabled and the BPL,

BP0, BP1,B P2, and TB bits in the STATUS register can

all be changed. As long as BPL bit is set to ‘0’ or WP#

pin is driven high (VIH) prior to the low-to-high transition

of the CE# pin at the end of the WRSR instruction, the

bits in the STATUS register can all be altered by the

WRSR instruction. In this case, a single WRSR instruction

can set the BPL bit to ‘1’ to lock down the STATUS reg-

ister as well as altering the BP0, BP1, BP2, and TB bits

at the same time. See Table 4-1 for a summary descrip-

tion of WP# and BPL functions.

FIGURE 5-12:

WRITE ENABLE (WREN) AND WRITE STATUS REGISTER (WRSR) SEQUENCE

MODE 3

High-Impedance

MODE 0

STATUS

7 6 5 4321 0

MSb

MSB

MODE 3

SCK

CE#

MODE 0

0 1 234 5 6 7

0 1 234 5 6 789 10 11 12 13 14 15

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