SST25WF080B datasheet(8/44 Pages) MICROCHIP

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SST25WF080B

DS20005164H-page 8

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4.2.4

BLOCK PROTECTION LOCK-DOWN

(BPL–BIT 7)

When the WP# pin is driven low (VIL), it enables the

Block Protection Lock Down (BPL) bit. When BPL is set

to ‘1’, it prevents any further alteration of the BP0, BP1,

BP2, TB, and BPL bits. When the WP# pin is driven

high (VIH), the BPL bit has no effect and its value is

‘Don’t Care’.

TABLE 4-3:

SOFTWARE STATUS REGISTER BLOCK PROTECTION

Protection Level

STATUS Register Bit

Protected Memory Address

BP2

BP1

BP0

0 (Full Memory Array unprotected)

None

T1 (1/16 Top Memory Block protected)

0F0000H-0FFFFFH

T2 (1/8 Top Memory Block protected)

0E0000H-0FFFFFH

T3 (1/4 Top Memory Block protected)

0C0000H-0FFFFFH

T4 (1/2 Top Memory Block protected)

080000H-0FFFFFH

B1 (1/16 Bottom Memory Block protected)

000000H-00FFFFH

B2 (1/8 Bottom Memory Block protected)

000000H-01FFFFH

B3 (1/4 Bottom Memory Block protected)

000000H-03FFFFH

B4 (1/2 Bottom Memory Block protected)

000000H-07FFFFH

5 (Full Memory Block protected)

000000H-0FFFFFH

5 (Full Memory Block protected)

000000H-0FFFFFH

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