SST25WF080B datasheet(6/44 Pages) MICROCHIP

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SST25WF080B

DS20005164H-page 6

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4.0.1

HOLD

In the hold mode, serial sequences underway with the

SPI Flash memory are paused without resetting the

clocking sequence. To activate the HOLD# mode, CE#

must be in active-low state. The HOLD# mode begins

when the SCK active-low state coincides with the fall-

ing edge of the HOLD# signal. The Hold mode ends

when the rising edge of the HOLD# signal coincides

with the SCK active-low state. HOLD# must not rise or

fall when SCK logic level is high. See Figure 4-2 for

Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-

impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active-high during a Hold condition, the

device returns to standby mode. The device can then

be re-initiated with the command sequences listed in

Table 5-1. As long as HOLD# signal is low, the memory

remains in the Hold condition. To resume communica-

tion with the device, HOLD# must be driven active-

high, and CE# must be driven active-low. See Figure 4-

2 for Hold timing.

FIGURE 4-2:

HOLD CONDITION WAVEFORM

4.1

Write Protection

SST25WF080B provides software Write protection. The

Write-Protect pin (WP#) enables or disables the lock-

down function of the STATUS register. The Block Pro-

tection bits (BP0, BP1, BP2, TB, and BPL) in the STA-

TUS register provide write protection to the memory

array and the STATUS register. See Table 4-3 for the

Block Protection description.

4.1.1

WRITE-PROTECT PIN (WP#)

The Write-Protect (WP#) pin enables the lock-down

function of the BPL bit (bit 7) in the STATUS register.

When WP# is driven low, the execution of the Write

STATUS Register (WRSR) instruction is determined by

the value of the BPL bit (see Table 4-1). When WP# is

high, the lock-down function of the BPL bit is disabled.

Active

Hold

Active

SCK

HOLD#

TABLE 4-1:

CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION

WP#

BPL

Execute WRSR Instruction

Not Allowed

Allowed

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