STPMIC25APQR datasheet(104/145 Pages) STMICROELECTRONICS

104 / 145 page

6.5.17

REFDDR PWRCTRL control register (REFDDR_PWRCTRL_CR)

Table 70. REFDDR_PWRCTRL_CR

PWRCTRL_DLY_H[1:0]

PWRCTRL_DLY_L[1:0]

PWRCTRL_SEL[1:0]

PWRCTRL_RST

PWRCTRL_EN

R/W

•

Address: 0x66

•

Default: 0x00

•

Description: REFDDR PWRCTRL control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

allocate a PWRCTRL signal for controlling the REFDDR (see Section 5.4.6).

[7:6]

PWRCTRL_DLY_H[1:0]: REFDDR control/reset source shift delay from low to High level

00: no delay

01: 1.5 ms delay

10: 3 ms delay

11: 6 ms delay

[5:4]

PWRCTRL_DLY_L[1:0]: REFDDR control/reset source shift delay from high to Low level

00: no delay

01: 1.5 ms delay

10: 3 ms delay

11: 6 ms delay

[3:2]

PWRCTRL_SEL[1:0]: REFDDR control/reset PWRCTRL source selection

00: No control source

01: PWRCTRL1 control source

10: PWRCTRL2 control source

11: PWRCTRL3 control source

[1]

PWRCTRL_RST: REFDDR independent reset source enable

0: no effect

1: reset enable (when the selected PWRCTRL source is active, REFDDR is disabled, and REFDDR control registers

are reset to the default value. When the selected PWRCTRL source is inactive, REFDDR operates according to

REFDDR_MAIN_CR. See Table 27)

[0]

PWRCTRL_EN: REFDDR control source enable

0: disable (REFDDR operates according to REFDDR_MAIN_CR)

1: enable (REFDDR operates according to REFDDR_MAIN_CR or REFDDR_ALT_CR depending on the PWRCTRL

selected source. See Table 27)

STPMIC25

DS14278 - Rev 3

page 104/145

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