ADAU1761BCPZ-R7 datasheet(44/92 Pages) AD

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Data Sheet

ADAU1761

DSP CORE

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Rev. F | 44 of 92

0000 0000 1100 1100 1100 1100 1101 = 0.1

0000 0010 0000 0000 0000 0000 0000 = 0.25

0000 1000 0000 0000 0000 0000 0000 = 1.0

0010 0000 0000 0000 0000 0000 0000 = 4.0

0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB)

The serial port accepts up to 24 bits on the input and is sign-ex-

tended to the full 28 bits of the DSP core. This allows internal gains

of up to 24 dB without internal clipping.

A digital clipper circuit is used between the output of the DSP core

and the DACs or serial port outputs (see Figure 68). This circuit

clips the top four bits of the signal to produce a 24-bit output with a

range of 1.0 (minus 1 LSB) to −1.0. Figure 68 shows the maximum

signal levels at each point in the data flow in both binary and

decibel levels.

Figure 68. Numeric Precision and Clipping Structure

PROGRAMMING

On power-up, the ADAU1761 must be configured with a clocking

scheme and then loaded with register settings. After the codec

signal path is set up, the DSP core can be programmed. There are

1024 instruction cycles per audio sample, resulting in an internal

clock rate of 49.152 MHz when fS = 48 kHz.

The part can be programmed easily using SigmaStudio, a graphical

tool provided by Analog Devices (see Figure 69). No knowledge

of writing line-level DSP code is required. More information about

SigmaStudio can be found at www.analog.com.

Figure 69. SigmaStudio Screen Shot

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