전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ADAU1761BCPZ-R7 데이터시트(PDF) 80 Page - Analog Devices

부품명 ADAU1761BCPZ-R7
상세설명  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADAU1761BCPZ-R7 데이터시트(HTML) 80 Page - Analog Devices

Back Button ADAU1761BCPZ-R7 Datasheet HTML 76Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 77Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 78Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 79Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 80Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 81Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 82Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 83Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 84Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 80 / 92 page
background image
Data Sheet
ADAU1761
CONTROL REGISTERS
analog.com
Rev. F | 80 of 92
Table 134. Serial Output Route Control Register (Continued)
Bits
Bit Name
Description
1100
Reserved
1101
ADCs [L, R] to serial output [R2, L2]
1110
Reserved
1111
ADCs [L, R] to serial output [R3, L3]
R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4)
The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, these
pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins.
Table 135.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
LRGP3
BGP2
SDOGP1
SDIGP0
Table 136. Table SEQ Table \* ARABIC 85 . Serial Data/GPIO Pin Configuration Register
Bits
Bit Name
Description
3
LRGP3
LRCLK or GPIO3 pin configuration select.
0 = LRCLK enabled (default).
1 = GPIO3 enabled.
2
BGP2
BCLK or GPIO2 pin configuration select.
0 = BCLK enabled (default).
1 = GPIO2 enabled.
1
SDOGP1
ADC_SDATA or GPIO1 pin configuration select.
0 = ADC_SDATA enabled (default).
1 = GPIO1 enabled.
0
SDIGP0
DAC_SDATA or GPIO0 pin configuration select.
0 = DAC_SDATA enabled (default).
1 = GPIO0 enabled.
R61: DSP Enable, 16,629 (0x40F5)
Table 137.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPEN
Table 138. DSP Enable Register
Bits
Bit Name
Description
0
DSPEN
Enables the DSP. Set this bit before writing to the parameter RAM and before setting the DSPRUN bit in Register R62 (Address 0x40F6).
0 = DSP disabled (default).
1 = DSP enabled.
R62: DSP Run, 16,630 (0x40F6)
Table 139.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPRUN



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com