ADAU1761BCPZ-R7 datasheet(52/92 Pages) AD

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Data Sheet

ADAU1761

CONTROL REGISTERS

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Rev. F | 52 of 92

Table 37. PLL Control Register (Continued)

Byte

Bits

Bit Name

Description

Setting

Value of X

1 (default)

Type

Type of PLL. When set to integer mode, the values of M and N are ignored.

0 = integer (default).

1 = fractional.

Lock

PLL lock. This read-only bit is flagged when the PLL has finished locking.

0 = PLL unlocked (default).

1 = PLL locked.

PLLEN

PLL enable.

0 = PLL disabled (default).

1 = PLL enabled.

R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)

Table 38.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

JDDB[1:0]

JDFUNC[1:0]

Reserved

JDPOL

Table 39. Digital Microphone/Jack Detection Control Register

Bits

Bit Name

Description

[7:6]

JDDB[1:0]

Jack detect debounce time.

Setting

Debounce Time

5 ms (default)

10 ms

20 ms

40 ms

[5:4]

JDFUNC[1:0]

JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital microphone input.

Setting

Pin Function

Jack detect off (default)

Jack detect on

Digital microphone input

Reserved

JDPOL

Jack detect polarity. Detects high or low signal.

0 = detect high signal (default).

1 = detect low signal.

R3: Record Power Management, 16,393 (0x4009)

This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADCs, record path

mixers, and PGAs can be set to one of four modes. These settings are normal operation, power saving mode, enhanced performance mode,

and extreme power saving mode. Each of these modes draws current from a central bias. Enhanced performance mode offers the highest

performance with the trade-off of higher power consumption.

Table 40.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

MXBIAS[1:0]

ADCBIAS[1:0]

RBIAS[1:0]

Reserved

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