전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ADAU1761BCPZ-R7 데이터시트(PDF) 82 Page - Analog Devices

부품명 ADAU1761BCPZ-R7
상세설명  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADAU1761BCPZ-R7 데이터시트(HTML) 82 Page - Analog Devices

Back Button ADAU1761BCPZ-R7 Datasheet HTML 78Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 79Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 80Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 81Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 82Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 83Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 84Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 85Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 86Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 82 / 92 page
background image
Data Sheet
ADAU1761
CONTROL REGISTERS
analog.com
Rev. F | 82 of 92
Table 144. Serial Port Sampling Rate Register (Continued)
Bits
Bit Name
Description
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved
R65: Clock Enable 0, 16,633 (0x40F9)
This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this register
to disable blocks that are not being used.
Table 145.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SLEWPD
ALCPD
DECPD
SOUTPD
INTPD
SINPD
SPPD
Table 146. Clock Enable 0 Register
Bits
Bit Name
Description
6
SLEWPD
Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are disabled and stay set to their
current state.
0 = powered down (default).
1 = enabled.
5
ALCPD
ALC digital clock engine enable.
0 = powered down (default).
1 = enabled.
4
DECPD
Decimator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
3
SOUTPD
Serial routing outputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
2
INTPD
Interpolator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
1
SINPD
Serial routing inputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
0
SPPD
Serial port digital clock engine enable.
0 = powered down (default).
1 = enabled.
R66: Clock Enable 1, 16,634 (0x40FA)
This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the ADCs,
DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in main mode. For maximum power
saving, use this register to disable clocks that are not being used.
Table 147.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
CLK1
CLK0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com