PM7344 datasheet(110/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Registers 00EH Clock Activity Monitor

Bit

Type

Function

Default

Bit 7

XCLKIA

Bit 6

RCLKI1A

Bit 5

RCLKI2A

Bit 4

RCLKI3A

Bit 3

RCLKI4A

Bit 2

TCLKIA

Bit 1

TFCLKA

Bit 0

RFCLKA

This register provides activity monitoring on S/UNI-MPH clock inputs.

XCLKA:

The XCLKA bit monitors for low to high transitions on the XCLK input.

XCLKA is set high on a rising edge of XCLK, and is set low when this register

is read.

RCLKI1A, RCLKI2A, RCLKI3A, RCLKI4A:

The RCLKIxA bits monitors for low to high transitions on the RCLKI[x] inputs.

RCLKIxA is set high on a rising edge of RCLKI[x], and is set low when this

TCLKIA:

The TCLKIA bit monitors for low to high transitions on the TCLKI input.

TCLKIA is set high on a rising edge of TCLKI, and is set low when this

TFCLKA:

The TFCLKA bit monitors for low to high transitions on the TFCLK input.

TFCLKA is set high on a rising edge of TFCLK, and is set low when this

RFCLKA:

The RFCLKA bit monitors for low to high transitions on the RFCLK input.

RFCLKA is set high on a rising edge of RFCLK, and is set low when this

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