EMC2101-R-ACZL-TR datasheet(32/56 Pages) MICROCHIP

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EMC2101

DS20006703A-page 32

 2022 Microchip Technology Inc. and its subsidiaries

5.14

TACH Reading Registers

The TACH Registers hold the 16-bit TACH Reading.

This reading represents the number of TACH counts

detected. The RPM of the fan can be determined by

Equation 5-2 (see also Appendix C: “TACH Refer-

ence Table”). The bit weighting of each TACH[15:0] bit

is shown in parenthesis after the value. When deter-

mining the final fan speed, the TACH[15:0] bits need to

be decoded into an equivalent decimal number.

EQUATION 5-2:

5.15

TACH Limit Registers

The TACH Limit Registers store the maximum TACH

count that the fan is expected to operate at. TACH

count is inversely proportional to the actual fan speed.

This limit is used to guarantee that the fan has spun up

properly. If the measured TACH is higher than this limit

(indicating that the fan speed is lower than the mini-

mum RPM value), then the TACH bit is set in the Status

Additionally if the measured TACH count exceeds this

limit, depending on the status of the TACH_M[1:0] bits

(see Section 5.16 “Fan Configuration Register”),

the TACH reading registers may be forced to FFFFh.

TACH READING REGISTERS (ADDRESSES 46h AND 47h)

Address

R/W

Default

46h

TACH

Reading

Low Byte

TACH7

(128)

TACH6

(64)

TACH5

(32)

TACH4

(16)

TACH3

(8)

TACH2

(4)

TACH1

(2)

TACH0

(1)

FFh

47h

TACH

Reading

High Byte

TACH15

(32768)

TACH14

(16384)

TACH13

(8192)

TACH12

(4096)

TACH11

(2048)

TACH10

(1024)

TACH9

(512)

TACH8

(256)

FFh

RPM

5 400 000



TACH_Count

----------------------------------

Where:

TACH_COUNT = the decimal representation of

the TACH[15:0] bits.

TACH READING LOW BYTE REGISTER (ADDRESSES 48h AND 49h)

Address R/W

Default

48h

R/W

TACH Limit

Low Byte

TACH_L7

TACH_L6

TACH_L5

TACH_L4

TACH_L3

TACH_L2

TACH_L1 TACH_L0

FFh

49h

R/W

TACH Limit

High Byte

TACH_L15

TACH_L14

TACH_L13

TACH_L12

TACH_L11 TACH_L10 TACH_L9 TACH_L8

FFh

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