EMC2101-R-ACZL-TR datasheet(14/56 Pages) MICROCHIP

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EMC2101

DS20006703A-page 14

 2022 Microchip Technology Inc. and its subsidiaries

4.4.1

ALERT/TACH AS A TEMPERATURE

COMPARATOR

When the ALERT/TACH pin is used as a temperature

comparator, the ALERT/TACH output is asserted when

an out of limit measurement (> high limit, < low limit or

> TCRIT limit) is detected on any diode (low limits only

apply to the external diode channel) or when the

external diode connections are open. When the

condition is no longer true, the ALERT/TACH output will

deassert. Reading from the Status Register will cause

the ALERT/TACH pin to be released however it will not

prevent it from being re-asserted based on the

temperature comparisons.

Setting the MASK bit will not affect the ALERT/TACH

pin when it is configured as a temperature comparator,

however the individual channel mask bits will block the

ALERT/TACH pin from being asserted.

4.4.2

ALERT/TACH AS AN INTERRUPT

When the ALERT/TACH pin is used as an interrupt

signal the pin is asserted whenever an out-of-limit

condition is detected. The ALERT/TACH pin will remain

asserted until it is cleared even if the error condition is

removed.

4.4.3

MASK BIT

The MASK bit behaves differently depending on which

mode the ALERT/TACH pin is configured to operate in.

If the EMC2101 is configured with the ALERT/TACH

pin operating in Interrupt Mode, the MASK bit will be set

in the following cases:

Automatically after the Status Register has been

read if any bits in the Status Register have been

set,

except

BUSY

and

FAULT

(see

Automatically when the EMC2101 responds to

an Alert Response Address (ARA) command on

an SMBus and the ALERT/TACH pin is

asserted. The ARA command does not clear the

Status Register. If the MASK bit is cleared prior

to reading and clearing the Status Register, then

the ALERT/TACH pin will be asserted.

Directly via the SMBus.

In Interrupt Mode, the MASK bit will block the ALERT/

TACH pin from being asserted in response to an error

condition.

If the EMC2101 is configured with the ALERT/TACH

pin operating in Comparator Mode, the MASK bit can

only be set via the SMBus. In this mode, setting the

MASK bit will not affect the ALERT/TACH pin.

In either mode, setting the individual channel mask bits

will block the appropriate channel from asserting the

ALERT/TACH pin.

10 kΩ ±5%

Host Load via SMBus

FAN output initialize to 0% Duty Cycle

18 kΩ ±5%

Auto Load via EEPROM

FAN output initialize to 100% Duty Cycle

33 kΩ ±5%

Auto Load via EEPROM

FAN output initialize to 0% Duty Cycle

TABLE 4-1:

ALERT/TACH PULL-UP RESISTORS SMBus/FAN MODE FOR EMC2101-R

(CONTINUED)

ALERT/TACH

Pull-up Resistor

SMBus Mode

FAN Mode

Polarity Bit Setting

(See Section 5.16, Fan

Configuration

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