EMC2101-R-ACZL-TR datasheet(33/56 Pages) MICROCHIP

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DS20006703A-page 33

EMC2101

5.16

Fan Configuration Register

The Fan Configuration Register enables the Fan

Control Look-Up Table and polarity of the PWM signal

driving the output.

FAN CONFIGURATION REGISTER (ADDRESS 4Ah)

U-0

R/W

—

FORCE

PROG

POLARITY

CLK_SEL

CLK_OVR

TACH_M[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

-n = Value at POR

‘1’ = bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

FORCE: Enables the External Temperature Force Register. This bit is not used if the Fan Control

Look-Up Table is not used.

1 = The External Temperature Force Register is used. When determining the position in the Fan

Control Look-Up Table, the contents of the External Temperature Force Register will be used instead

of the measured External Diode temperature. All limits will be checked against the measured External

Diode temperature as normal.

0 = (default) The External Diode Force Register is not used. The measured External Diode

temperature is used to determine the position in the Fan Control Look-Up Table.

bit 5

PROG: Enables the Fan Control Look-Up Table for update and sets fan driver output based on Fan

Control Look-Up Table values.

1 = (default) The Fan Setting Register and Fan Control Look-Up Table Registers can be written. The

value written into the Fan Setting Register will be instantly applied to the fan driver and the Fan Control

Look-Up Table will not be used.

0 = The Fan Setting Register and Fan Control Look-Up Table Registers are read-only and the Fan

Control Look-Up Table Registers will be used.

bit 4

POLARITY: Sets the polarity of the Fan output driver. For the EMC2101-R, the value of this bit is

determined by the value of the pull-up resistor on the ALERT/TACH pin (see Table 4-1). When the

PWM default value is set at 100% duty cycle, the default value is set to ‘1’ and when the PWM default

value is set to 0% duty cycle, the default value is set to ‘0’. This occurs within 10 ms after power-up.

1 = The polarity of the Fan output driver is inverted. A ‘00h’ setting will correspond to a 100% duty

cycle or maximum DAC output voltage.

0 = (default) The polarity of the Fan output driver is noninverted. A ‘00h’ setting will correspond to a

0% duty cycle or minimum DAC output voltage.

bit 3

CLK_SEL: Determines the base clock that is used to determine the final PWM frequency.

1 = The base clock that is used to determine the PWM frequency is 1.4 kHz.

0 = (default) The base clock that is used to determine the PWM frequency is 360 kHz.

bit 2

CLK_OVR: Overrides the CLK_SEL bit and uses the Frequency Divide Register to determine the

base PWM frequency. It is recommended that this bit be set for maximum PWM resolution.

1 = The base clock that is used to determine the PWM frequency is set by the Frequency Divide

0 = (default) The base clock frequency for the PWM is determined by the CLK_SEL bit.

bit 1-0

TACH_M: Determines the basic operation of the tachometer input as shown in Table 5-4.

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