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RT3612EB 데이터시트(PDF) 35 Page - Richtek Technology Corporation |
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RT3612EB 데이터시트(HTML) 35 Page - Richtek Technology Corporation |
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35 / 47 page ![]() RT3612EB 35 DS3612EB-02 December 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 20. Undershoot Suppression Behavior in PS0 Figure 21. Undershoot Suppression Behavior in PS1 VRAMP Positive offset VCOMP Load PWM High Frequency ACLL Voltage Compensation RT3612EB provides positive offset to enhance performance that only applies to high frequency ACLL. The positive offset can be set through PIN-SETTING in PS1. HFACLL_LIFT_PS1[1:0] is the related settings. The related setting table is listed in Table 15. The default set of HFACLL_LIFT_PS1[1:0]=00. Note that smaller setting value represents higher positive offset. The final setting must be based on actual measurement. HFACLL_LIFT_PS1 [1:0] High Frequency ACLL Voltage C0mpensation in PS1 (index) 00 60 01 80 10 100 11 Disable Table 15. PIN-SETTING of High Frequency ACLL Voltage Compensation in PS1 VRAMP Positive offset VCOMP Load PWM |
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