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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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RT3612EB 데이터시트(PDF) 18 Page - Richtek Technology Corporation |
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RT3612EB 데이터시트(HTML) 18 Page - Richtek Technology Corporation |
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18 / 47 page  RT3612EB 18 DS3612EB-02 December 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 1. Summary of Pin Setting Functions Function Setting Symbol Description SET1 Divider Register[4] TON width setting (Switching frequency) TONSET[3] According to required frequency, to select TON width. Divider Register[3:0] ICCMAX ICCMAX[3:0] According to platform, to set corresponding ICCMAX. IXR Register[4:2] TON width setting (Switching frequency) TONSET[2:0] According to required frequency, to select TON width. IXR Register[1] VBOOT VBOOT_SET VBOOT_SET= 0: VBOOT = 0V, wait for SVID command after controller power on. VBOOT_SET= 1: Automatically DVID to VBOOT=1.8V after controller power on. SET2 Divider Register[4:2] Anti-overshoot trigger level ANTIOVS_TH[2:0] ANTIOVS for reduction of overshoot at loading falling edge. To set trigger level. Divider Register[1:0] Current gain Ai[1:0] Current gain setting IXR Register[4] DVID fast slew rate DVID Fast_SR DVID Fast_SR = 0 : 48mV/us; for Y/U/H-line. IXR Register[3] Acoustic noise suppression ANS_EN ANS_EN=0 : Disable. ANS_EN=1 : Enable. To reduce acoustic noise. IXR Register[2:1] High frequency ACLL voltage compensation in PS1 HFACLL_LIFT _PS1[1:0] To provide positive offset in high frequency ACLL. SET3 Divider Register[4:2] Adaptive quick response(AQR) trigger level AQR_TH[2:0] AQR for loop response speed-up of loading rising edge. To set trigger level. Divider Register[1:0] Zero current detection threshold ZCD_TH[1:0] Detects whether each phase current crosses zero current. To set trigger level. IXR Register[4] Sum OCP ratio SUM_OC SUM_OC = 0 : 160% x ICCMAX SUM_OC = 1 : 130% x ICCMAX IXR Register[3:1] Undershoot suppression UDS[2:0] To improve undershoot by applying a positive offset at loading edge. To set trigger level. TSEN Divider Register[5] Advanced ramp magnitude in PS1 FLRAMP_PS1 Advanced Ramp is developed to solve loop natural lag due to PCB parasitic inductance and prevent adjacent PWM turn-on. Divider Register[4:3] Advanced ramp magnitude in PS0 FLRAMP_PS0[1:0] Advanced Ramp is developed to solve loop natural lag due to PCB parasitic inductance and prevent adjacent PWM turn-on. Divider Register[2] Zero load line Zero LL_EN Zero LL_EN = 0 : Disable zero load line. Zero LL_EN = 1 : Enable zero load line. Divider Register[1] DVID voltage compensation level DVID_LIFT DVID_LIFT = 0 : Disable. DVID_LIFT = 1 : 5uA current source sinks from FB pin. |
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