RT3612EB datasheet(40/47 Pages) RICHTEK

40 / 47 page

RT3612EB

DS3612EB-02 December 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Acoustic Noise Suppression

The RT3612EB support acoustic noise suppression

function for reducing acoustic noise induced by

Piezoelectric Effect from MLCC. As output voltage

transition, especially in Dynamic VID, the vibrating MLCC

produces acoustic noise if the vibrating frequency falling

into audible band and the noise level is related to the output

voltage transition amplitude

ΔV. Therefore, the RT3612EB

adapts acoustic noise suppression function which is

enabled by PIN-SETTING of ANS_EN = 1.

Over Current Protection (OCP)

The RT3612EB has two OCP mechanisms, sum OCP

and per phase OCP.

Sum OCP

The threshold of sum OCP for PS0 is defined as

SUM OC PS0

CSx

SOCP

ICCMAX

IMON EQ

KVIMON

DCR R





PS1/2/3 sum OCP is defined as

SUM OC PS1

CSx

SOCP

ICCMAX

IMON EQ

0.5 K

VIMON

DCR R





While RIMON,EQ is designed exactly for

ICCMAX

IMON,EQ

CSx

ICCMAX

DCR

VIMON

= ICCMAX

VIMON

=1.6V



And KSOCP = 1.3 and 1.6. It is set by Pin Setting Function

of SET3.

Sum OCP threshold can be simplified as ISUM_OC,PS0 =

KSOCP x ICCMAX and ISUM_OC,PS1 = 0.5 x KSOCP x ICCMAX

when ICCMAX >= 45A. and ISUM_OC,PS0 = ISUM_OC,PS1 =

KSOCP x ICCMAX when ICCMAX < 45A . While inductor

current above sum OCP threshold lasts 40

μs, controller

de-asserts VR_READY and latches PWM in tri-state to

turn off high-side and low-side power MOSFETs.

Per Phase OCP

Per phase OCP is mainly for short circuit protection. Per

phase OCP threshold is directly linked with ICCMAX. The

relations between per phase OCP threshold, I _Max

Table 17. While inductor current exceeds per phase OCP

threshold, PWMs high pulse are blanked untill the inductor

current is pulled below per phase OCP threshold. If the

POCP indicator keeps high for 40

μs ( with 10μs deglitch

), the controller de-asserts VR_READY and latches PWM

in tri-state to turns off both the high-side and low-side

MOSFETs. OCP_SUM is masked during DVID period and

μs after VID settles. All of the OCP protections are

illustrated in Figure 27 and Figure 28.

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