DSP56303 datasheet(218/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

9-26

Freescale Semiconductor

Triple Timer Module

7–4

TC[3–0]

Timer Control

Control the source of the timer clock, the behavior of the TIO signal, and the

Timer mode of operation. Section 9.3, Operating Modes, on page 9-5

describes the timer operating modes in detail. To ensure proper operation,

the TC[3–0] bits should be changed only when the timer is disabled (that is,

when the TCSR[TE] bit is cleared).

Note:

If the clock is external, the counter is incremented by the transitions

on the TIO signal. The external clock is internally synchronized to

the internal clock, and its frequency should be lower than the

internal operating frequency divided by 4 (that is, CLK/4).

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Number

Mode

Function

TIO

Clock

Timer and

GPIO

Internal

Timer pulse

Outpu

Internal

Timer toggle

Outpu

Internal

Event counter

Input

Externa

Input width

measurement

Input

Internal

Input period

measurement

Input

Internal

Capture

event

Input

Internal

Pulse width

modulation

Outpu

Internal

Reserved

—

Watchdog

pulse

Outpu

Internal

Watchdog

Toggle

Outpu

Internal

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Note:

The GPIO function is enabled only if all of the TC[3–0] bits are 0.

Reserved. Write to zero for future compatibility.

Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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