DSP56303 datasheet(74/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-16

Freescale Semiconductor

Core Configuration

Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)

The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt

priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest

priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL bits.

The IPRC also selects the trigger mode of the external interrupts (IRQA–IRQD). If the value of the

IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is

negative-edge-triggered.

4.4.2 Interrupt Table Memory Map

Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries for

interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The

DSP56303 initialization program loads the table entry for each interrupt serviced with two

interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are used

for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for

host NMI (IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector locations can

be used for program or data storage.

Table 4-4. Interrupt Priority Level Bits

IPL bits

Interrupts Enabled

Interrupts Masked

Interrupt Priority Level

xxL1

xxL0

—

Yes

0, 1

Yes

0, 1, 2

HPL0

HPL1

S0L0

S0L1

S1L0

S1L1

HI08 IPL

ESSI0 IPL

ESSI1 IPL

SCI IPL

TRIPLE TIMER IPL

T0L0

T0L1

SCL0

SCL1

reserved

Reserved bit; read as zero; should be written with zero for future compatibility

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