DSP56303 datasheet(32/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

2-8

Freescale Semiconductor

Signals/Connections

Table 2-9. Interrupt and Mode Control

Signal Name

Type

State During

Reset

Signal Description

RESET

Input

Reset

Deassertion of RESET is internally synchronized to the clock out

(CLKOUT). When asserted, the chip is placed in the Reset state and the

internal phase generator is reset. The Schmitt-trigger input allows a slowly

rising input (such as a capacitor charging) to reset the chip reliably. If

RESET is deasserted synchronous to CLKOUT, exact start-up timing is

guaranteed, allowing multiple processors to start and operate

synchronously. When the RESET signal is deasserted, the initial chip

operating mode is latched from the MODA, MODB, MODC, and MODD

inputs. The RESET signal must be asserted after power-up.

RESET can tolerate 5 V.

MODA/IRQA

Input

Mode Select A/External Interrupt Request A

Selects the initial chip operating mode during hardware reset and becomes

a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA/IRQA MODA, MODB,

MODC, and MODD select one of sixteen initial chip operating modes,

latched into the OMR when the RESET signal is deasserted.

Internally synchronized to CLKOUT. If IRQA is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQA to exit the Wait state. If a STOP instruction

puts the processor is in the Stop standby state and IRQA is asserted, the

processor exits the Stop state.

MODA/IRQA can tolerate 5 V.

MODB/IRQB

Input

Mode Select B/External Interrupt Request B

Selects the initial chip operating mode during hardware reset and becomes

a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into OMR

when the RESET signal is deasserted.

Internally synchronized to CLKOUT. If IRQB is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQB to exit the Wait state.

MODB/IRQB can tolerate 5 V.

MODC/IRQC

Input

Mode Select C/External Interrupt Request C

Selects the initial chip operating mode during hardware reset and becomes

a level-sensitive or negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA, MODB, MODC, and

MODD select one of sixteen initial chip operating modes, latched into OMR

when the RESET signal is deasserted.

Internally synchronized to CLKOUT. If IRQC is asserted synchronous to

CLKOUT, multiple processors can be re-synchronized using the WAIT

instruction and asserting IRQC to exit the Wait state.

MODC/IRQC can tolerate 5 V.

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