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Phase Lock Loop (PLL)

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

2-5

2.4 Phase Lock Loop (PLL)

2.5 External Memory Expansion Port (Port A)

Note:

When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases bus

mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],

AA0

/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.

2.5.1 External Address Bus

Table 2-5. Phase Lock Loop Signals

Signal Name

Type

State During

Reset

Signal Description

PCAP

Input

PLL Capacitor

Connects an off-chip capacitor to the PLL filter. See the DSP56303

Technical Data sheet to determine the correct PLL capacitor value.

Connect one capacitor terminal to PCAP and the other terminal to VCCP.

If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.

CLKOUT

Output

Chip-driven

Clock Output

Provides an output clock synchronized to the internal core clock phase.

If the PLL is enabled and both the multiplication and division factors

equal one, then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency of

EXTAL.

PINIT/NMI

Input

PLL Initial/Non-Maskable Interrupt

During assertion of RESET, the value of PINIT/NMI is written into the PLL

Enable (PEN) bit of the PLL control register, determining whether the

PLL is enabled or disabled. After RESET deassertion and during normal

instruction processing, the PINIT/

NMI Schmitt-trigger input is a

negative-edge-triggered Non-Maskable Interrupt (NMI) request internally

synchronized to CLKOUT.

PINIT/NMI can tolerate 5 V.

Table 2-6. External Address Bus Signals

Signal

Name

Type

State During Reset,

Stop, or Wait

Signal Description

A[0–17]

Output

Tri-stated

Address Bus

When the DSP is the bus master, A[0–17] specify the address for

external program and data memory accesses. Otherwise, the signals

are tri-stated. To minimize power dissipation, A[0–17] do not change

state when external memory spaces are not being accessed.

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