TMP93CS41 datasheet(59/248 Pages) TOSHIBA

59 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-57

Figure 3.5.1 shows an example of an interface circuit using some of the pins described in

Table 3.5.4, in a case when the bus releasing function is used.

When the bus is released, neither internal memory nor internal I/O can be accessed. However,

the internal I/O continues to operate, so the watchdog timer (WDT) also continues to run.

Therefore, be careful about bus releasing time and setting of the detection time of the WDT.

Figure 3.5.1 Example of an Interface Circuit using the Bus Releasing Function

A circuit like the one shown above is needed to fix the signal level in the case when the bus is

released.

Resetting sets P30 ( RD ) and P31 ( WR ) to output; P40 ( CS0 ), P41 ( CS1 ), P32 ( HWR ), P36

(

R/ ), P37 ( RAS ), and P35 ( BUSAK ) all to input with pull-up resistor; as well as P42 ( CS2 )

and P20 to P27 (A16 to A23) to input with pull-down resistor.

A circuit like the one above is also needed to fix the signal level after resetting, because of the

possibility of conflict between the external pull-up resistor and the internal pull-down resistor.

The resistance of the external pull-up resistor must be 3 to 5 k

Ω, and the resistance of the

internal pull-down resistor is about 50 to 150 k

Ω.

Using a pull-down resistor is recommended for P20 to P27 (A16 to A23); however, if this is not

possible, a switching circuit like the one used for P42 ( CS2 ) may be used.

P20 (A16)

P27 (A23)

P30 ( RD )

P31 ( WR )

P32 ( HWR )

P36 (

)

P37 ( RAS )

P40 ( CS0 )

P41 ( CS1 )

P35 ( BUSAK )

3 to 5 k

Ω

System control bus

Address bus (A23 to A16)

P42 ( CS2 )

TMP93CS41 데이터시트(PDF) 59 Page - Toshiba Semiconductor